Ensuring Security in Semiconductor Design through Verification

Authors

  • Niranjana Gurushankar Hardware Verification Engineer at Cisco Systems, USA  Author

DOI:

https://doi.org/10.47363/JBBER/2023(1)E101

Keywords:

Semiconductor Security, Verification, Formal Verification, Simulation-Based Verification, Hardware-Assisted Verification, Post-Silicon Validation, Machine Learning

Abstract

The ever-growing complexity of semiconductor designs, the demand for powerful and feature-rich electronics, presents a significant challenge in ensuring their correctness and security. Security verification has become a critical process in the semiconductor design lifecycle, aiming to identify and mitigate potential vulnerabilities that could be exploited. Given the increasing reliance on semiconductor devices for critical infrastructure and applications, the importance of robust security verification cannot be overstated. This paper explores few of the crucial role verification plays in guaranteeing security within semiconductor design. It examines various facets of this process, including analyzing potential security threats and vulnerabilities. This paper delves into the critical role of verification in ensuring semiconductor security. It also explores various verification techniques, discusses emerging trends, and outlines future directions in this crucial field.

Author Biography

  • Niranjana Gurushankar, Hardware Verification Engineer at Cisco Systems, USA 

    Hardware Verification Engineer at Cisco Systems, USA 

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Published

2023-04-21